1. Field of the Invention
This invention relates to a capacitor element which is used for constituting a solid electrolytic capacitor such as tantalum capacitor or aluminum capacitor. The present invention also relates to a compacting device and method used for making such a capacitor element.
2. Description of the Prior Art
For conveniently explaining the problems to be solved by the present invention, reference is made to FIGS. 17 through 28 of the accompanying drawings.
FIGS. 17 and 18 show a typical prior art solid electrolytic capacitor 100. Such a capacitor is called a package-type capacitor and disclosed in Japanese Patent Application laid-open No. 60(1985)-220922 for example.
Specifically, the prior art capacitor 100 comprises a capacitor element 1 which includes a sintered porous chip 2 and an anode wire 3 projecting from one end of the chip 2. The chip 2 is covered by a cathode layer 6 paired with the anode wire 3. The anode wire 3 is connected to an anode lead 4 by welding for example, whereas the cathode layer 6 is electrically connected directly to a cathode lead 5. Further, a resin package 7 is formed to enclose the capacitor element 1 together with part of the anode and cathode leads 4, 5. The portions of the respective leads 2, 5 projecting from the package 7 may be bent toward the underside of the package 7 for conveniently mounting onto a surface of a circuit board (not shown), as indicated by phantom lines in FIG. 17.
FIG. 19 shows another prior art solid electrolytic capacitor 200 which is similar to the one illustrated in FIGS. 17 and 18 but differs therefrom mainly in that the cathode layer 6 is electrically connected to the cathode lead 5 indirectly via a safety fuse 8 which may be an overcurrent fuse or a temperature fuse. Further, the fuse 8 may be partially enclosed in an arc-extinguishing resin member 8a. Such a capacitor is disclosed in Japanese Patent Application Laid-open No. 2(1990)-105513 for example.
In either one of the prior art capacitors 100, 200, the capacitor element 1 is produced in the following manner.
Specifically, use is made of a compacting device, as shown in FIGS. 26 to 28. The compacting device comprises a form C having a shaping bore D of an entirely constant cross-sectional area, a lower die E, and an upper die G. Both of the dies E, G are vertically movable into and out of the shaping bore 12 of the form 11. Further, the upper die G is designed to removably hold an anode wire 3.
For compacting, a predetermined amount of metal powder (e.g. tantalum particles) F is loaded into the shaping bore D of the form C with the lower die E slightly inserted into the shaping bore D from below, as shown in FIG. 26.
Then, as shown in FIG. 27, the upper die G holding the anode wire 3 is inserted downwardly into the shaping bore D, whereas the lower die E is further advanced upwardly. As a result, the metal powder is compacted into a porous chip 2 with the anode wire 3 partially inserted in and partially projecting from the chip 2.
Then, as shown in FIG. 28, the upper die G is drawn upwardly out of the shaping bore D while the lower die E is additionally advanced upwardly past the shaping bore D. As a result, the chip 2 is pushed out of the shaping bore D. The chip 2 may have a square cross section of a side length d0 which is entirely constant from a top surface 2a to a bottom surface 2b, as shown in FIG. 20. The side surfaces 2c of the chip 2 are therefore parallel to a central longitudinal axis 2d of the chip 2 along which the anode wire 3 extends.
The porous chip 2 thus obtained is then subjected to sintering. Further, as shown in FIG. 21, the sintered chip 2 together with a root portion of the anode wire 3 is immersed in an aqueous solution A of phosphoric acid and subjected to anodic oxidation (electrolytic oxidation) by applying a direct current. As a result, a dielectric coating (made of e.g. tantalum pentoxide) is formed on the surfaces of the metal particles and on the immersed root portion of the anode wire 3. In FIG. 21, only the exposed portion of the dielectric coating is schematically represented by reference numeral 9 in an exaggerated manner for purposes of illustration.
Then, as shown in FIG. 22, the dielectrically coated chip 2 is immersed in an aqueous solution B of manganese nitrate to cause permeation of the solution into the porous chip portion, and thereafter taken out of the solution for baking. This step is repeated plural times to fill the inner voids or porous of the chip 2 with a solid electrolyte (e.g. manganese dioxide) while also forming an exposed solid electrolyte layer 6a over the exposed dielectric coating 4. It should be appreciated that a combination of some cathode side layers is shown as the single cathode layer 6 only for the convenience of illustration.
Then, as shown in FIG. 23, a metallic cathode layer 6 (made of silver or nickel for example) is formed to cover the bottom surface 2b and side surfaces 2c of the chip 2 usually with an intervening layer (e.g. graphite layer) interposed between the cathode layer 6 and the electrolyte layer. It should be appreciated that a combination of the cathode side layers (including the electrolyte layer 6a, the cathode layer 6, and etc.) is shown as the single cathode layer only for the convenience of illustration.
The prior art described above has been found to be disadvantageous in the following respects.
When the cross-section or outer dimension d0 of the chip 2 is rendered constant over the entire length of the chip (FIG. 20), the cathode layer 6 has a tendency to flare downward, as shown in FIG. 23. Such a tendency is attributable to the fact that a portion of the manganese nitrate solution deposited on the chip 2 tends to gravitationally move downward at the time of drying the deposited solution for forming the solid electrolyte layer 6a. Thus, a maximum outer dimension d0max will result at the bottom 2b of the chip 2.
On the other hand, it has been found that the anode wire 3 is liable to bending at the time of connecting to the anode lead 4, so that the central longitudinal axis 2d of the chip 2 may be inclined upwardly or downwardly by an angle .alpha.1 or .alpha.2 (FIG. 24), and/or laterally by an angle .beta.1 or .beta.2 (FIG. 25). Thus, if the cathode layer 6 flares in a direction away from the anode wire 3, the minimum wall thickness T1a, T1b, T2c or T2d of the resin package 7 at either of the four sides of the capacitor element 1 (i.e., four side surfaces 7a, 7b, 7c, 7d of the resin package 7) may become unacceptably small, resulting in a rejectable product. Otherwise, the volume of the chip 2 must be reduced, thereby hindering an increase of the realizable capacitance.
Due to the constant cross section of the chip 2 (see FIG. 20), the cross section of the shaping bore D (see FIGS. 26-28) is also made constant over the entire length thereof. Thus, when pushed out of the shaping bore D after compacting, the porous chip 2 is inevitably rubbed against the shaping bore D which may be rough-surfaced. As a result, the surfaces of the porous chip 17 may be clogged up by such rubbing, thereby hindering permeation of the maganese nitrate solution B (see FIG. 22) into the porous chip 2 or expelling of inside gases at the time of electrolyte formation. Further, the rubbing between the chip 2 and the shaping bore D is also disadvantageous in that the form C is easily damaged to shorten its own service life.
Moreover, since the degree of the rubbing increases as the degree of compaction increases, it has been conventionally difficult to increase the degree of compaction which is required for increasing the realizable capacitance of the product.